1. Field of the Invention
The present invention relates to a technique for recording and reproducing digital audio signal by a helical scan type video tape recorder together with a video signal.
2. Description of Prior Art
In a conventional helical scan type video tape recorder, a servo system is designed to synchronize with a vertical synchronization signal of a video signal. Accordingly, if a digital signal having a sampling frequency of 48 kHz, for example, is to be recorded together with the video signal, the number of samples of a digital signal in one vertical period is given by EQU 48 K/59.94=800.8
Accordingly, a method has been proposed (JP-A-61-233472) in which a data frame which can contain 800+.alpha. samples in one vertical period is secured, the digital signal is sectioned by a period at which a vertical synchronization signal is synchronized with a sampling frequency of the digital signal to form one data frame, and it is recorded together with a rate signal representing the number of samples in one data frame. Assuming now that n samples of data are recorded in one frame, dummy data of "0" pattern is recorded for the remaining 800+.alpha.-n samples of data in order to keep the record rate constant.
The above prior art digital signal recording/reproducing apparatus is explained with reference to drawings.
FIG. 3 shows a configuration of the prior art digital signal recording/reproducing apparatus. In FIG. 3, numeral 21 denotes an input terminal for a digital information signal, numeral 22 denotes a time axis converter, numeral 23 denotes an encoder, numeral 24 denotes a format controller, numeral 25 denotes a modulator, numeral 26 denotes a recording amplifier, numeral 27 denotes a rotating head, numeral 28 denotes a reproducing amplifier, numeral 29 denotes a demodulator, numeral 30 denotes a reverse-formatting controller, numeral 31 denotes a decoder, numeral 32 denotes a time axis reverse converter, numeral 33 denotes an output terminal for a digital information signal, numeral 34 denotes a switch, and a, b, and c respectively denote a head switching signal, a first rate discrimination signal and a second rate discrimination signal.
The operation of the above prior art digital signal recording/reproducing apparatus is now explained.
The digital information signal having a sampling frequency of 48 kHz applied to the input terminal 21 is sectioned in the time axis converter 22 by a period at which the head switching signal a synchronized with a vertical synchronization signal of the video signal is synchronized by a sampling clock so that it is divided into 800 or 801 samples of data frame Hereinafter, they are called frame A and frame B, respectively. Since the head switching signal is used as a reference, an average number of samples in one data frame is given by EQU 48 K/59.94=800.8
In the frame A, dummy data is inserted to make the number of samples conform to that of the frame B. A first rate discimination signal b is produced as information representing the number of samples in one data frame. The data output of the time axis converter 22 is interleaved by the encoder 23, and redundant data for error correction is added The output of the encoder 23, together with the first rate discrimination signal b, are converted to a predetermined record format by the formatting controller 24 which compresses it into data period for each data frame In an ample period, a fixed pattern having a number of inverted edges after data modulation is produced by the formatting controller 24 so that the demodulator 31 can quickly pull in the clock synchronized with the recorded data in the reproduction mode. FIG. 10 shows a conceptual view of the ample period and the data period. The modulator 25 modulates the output of the formatting controller by 8-10 conversion or NRZ conversion, and the modulated data is supplied to the rotating head 27 through the recording amplifier 26 and the switch 34, and recorded on a magnetic tape.
In the reproduction mode, the signal reproduced by the rotating head 27 is supplied to the demodulator 29 through the switch 34 and the reproducing amplifier 28, and processed in the reverse manner by the demodulator 29, reverse-formatting controller 30, decoder 31 and time axis reverse converter, and a digital information signal is produced at the output terminal 33. The reverse-formatting controller 30 detects from the reproduced signal a second rate discrimination signal c which represents the number of samples in one data frame, and the reverse-time axis converter 32 determines the data frame as either A or B based on the second rate discrimination signal c and carries out the reverse-time axis conversion.
FIG. 4 shows a configuration of the reverse-time axis converter 32. In FIG. 4, numeral 41 denotes a buffer memory, numeral 42 denotes a frequency divider, numeral 43 denotes a phase comparator, numeral 44 denotes a low-pass filter and numeral 45 denotes a voltage controlled oscillator.
The operation of the time axis reverse converter 32 is explained with reference to FIG. 4. The digital information signal which has been error-corrected and decoded by the decoder 31 is temporarily stored in the buffer memory 41. The frequency divider 42 receives the second rate discriminator c and frequency-divides the output clock of the voltage controlled oscillator 45 by 801 for the data frame B and by 800 for the data frame A. The phase comparator 43 compares phases of the head switching signal a and the output of the frequency divider 42 and produces a voltage proportional to the phase difference. The low-pass filter 44 eliminates a high frequency component and the voltage controlled oscillator 45 has its oscillation frequency controlled by the output voltage of the low-pass filter 44. The digital information signal is read from the buffer memory 41 by the output clock of 48 kHz from the voltage controlled oscillator 45 reproduced by the phase synchronization loop comprising the frequency divider 42, the phase comparator 43, the low-pass filter 44 and the voltage controlled oscillator 45.
In the above conventional digital signal recording/reproducing apparatus, when the vertical synchronization signal of the video signal is at 59.94 Hz, the number of samples in one data frame is 800 or 801 in principle. However, since the reproduced video signal of the VTR includes jitter, the vertical synchronization signal deviates from 59.94 Hz and the error amounts up to 0.5% as the damping is repeated. If the digital signal is recorded together with such a video signal, the number of samples in one data frame may assume one of the following multiple values ##EQU1## As a result, the rate information needs several bits to represent the multi-value information.
When the information thus recorded is reproduced, if the rate discrimination signal representing the number of samples is misdetected, for example, if the data frame having 800 samples is misdetected as the data frame having 801 samples, dummy data is included in the output digital audio data so that noise is generated.
In the time axis reverse converter, the phase synchronization loop for reproducing the sampling clock of 48 kHz of the digital data includes the frequency divider which has a large frequency division factor of around 800. As a result, a high loop gain is not attained and a phase pull-in time is long.
In addition, a band restriction condition is imposed because the recorded output of the digital signal recording/reproducing apparatus is recorded in the same track as the video signal track by frequency multiplexing or overwriting. Where a four-phase phase modulation (QPSK) or an offset four-phase phase modulation (O-QPSK) is used and a band-pass filter is used in the reproduction mode to pass only the predetermined frequency components to effect QPSK or O-QPSK demodulation, the following problems arise.
Assuming that f.sub.c is a carrier frequency for the QPSK or O-QPSK modulation, f.sub.s is a sampling frequency of digital data to be modulated, f.sub.c .+-.f.sub.B is a band-pass width of the band-pass filter (FIG. 5a) and an ample pattern is an all-"1" pattern, the band width after the modulation is given by ##EQU2## (FIG. 5b). When ##EQU3## the reproduced waveform cannot be extracted by the band-pass filter for the QPSK or O-QPSK demodulation because of group delay and phase distortion around a cutoff point of the band-pass filter. The QPSK or O-QPSK demodulation can be well attained if the ample pattern is an all-"0" pattern (which is all-"1" or all-"0" pattern after the NRZI conversion) because a spectrum after the modulation is that shown in FIG. 5c. However, the data clock is not reproduced because there is no reversal edge of a bit boundary in the reproduced data after the demodulation.